MRF Timing System Reference

Introduction:

• The MRF Timing System
• Examples of usage scenarios

Hardware:

• Event Master
• Fanout and Concentrator
• Event Generator
  • Event Generation
  • Distributed Bus
  • Timestamping support
  • Configurable Size Data Buffer
  • Programmable Outputs
  • Utility Functions in the Event Generator
  • Front Panel TTL Input with Phase Monitoring
  • Event Clock RF Source
• Delay Compensation
  • Topology ID
  • Active Delay Compensation
• EVG Function Register Map
  • Register descriptions
  • Front Panel Input Phase Monitoring Registers
  • Embedded Event Receivers
• MTCA-EVM-300
  • TTL Input Levels
  • Register Mapping
• EVM Firmware Version Change Log
• FCT Function Register Map
  • Status Register
  • Control Register
• Event Receiver
  • Functional Description
  • Event Decoding
  • Heartbeat Monitor
  • Event FIFO and Timestamp Events
  • Event Log
  • Distributed Bus and Data Transmission
  • Pulse Generators
  • Prescalers
  • Programmable Front Panel, Universal I/O and Backplane Connections
  • Flip-flop Outputs (from FW version 0E0207)
  • Front Panel Universal I/O Slots
  • GTX Pulse Mode
  • GTX Frequency Mode
  • GTX Pattern Mode
  • Configurable Size Data Buffer (EVR)
  • Segmented Data Buffer
  • Interrupt Generation
  • External Event Input
  • Programmable Reference Clock
  • Fractional Synthesiser
• MTCA-EVR-300
• VME-EVR-300
  • VME-EVR-300 Front Panel Connections
• Event Receiver Registermap
  • Register Map
  • Status Register
  • Control Register
  • Interrupt Flag Register
  • Interrupt Enable Register
  • Hardware Interrupt Mapping Register
  • Software Event Register
  • PCI Interrupt Enable Register
  • Receive Data Buffer Control and Status Register
  • FPGA Firmware Version Register
  • Clock Control Register
  • SPI Configuration Flash Registers
  • Delay Compensation Status Register
  • Sequence RAM Control Register
  • Prescaler Pulse Trigger Registers
  • Distributed Bus Pulse Trigger Registers
  • Pulse Generator Registers
  • Input Mapping Registers
  • Data Buffer Segment Interrupt Enable Register
  • Data Buffer Checksum Flag Register
  • Data Buffer Receive Flag Register
  • SFP Module EEPROM and Diagnostics
  • Hardware Configuration Summary
  • PCIe-EVR-300DC and IFB-300 Connections
  • mTCA-EVR-300 Connections
  • PCIe-EVR-300DC Firmware Upgrade
• EVR Firmware Version Change Log

mrfioc2 EPICS driver:

• Epics device driver for MRF Event Generator (EVG)
  • The Source
  • IOC Deployment
  • Classes/Sub-Components
  • EVG Device Support Reference
• EPICS device driver for MRF Event Receiver (EVR)
  • What is Available?
  • Prerequisites
  • Overview of the Driver
  • Receiver Functions
  • IOC Deployment
  • VME64x Device Configuration
  • PCI Device Configuration
  • Example Databases
  • Testing Procedures
  • Firmware Update
  • NTPD Time Source
  • Buffered Timestamp Capture
  • Implementation Details
  • EVR Device Support Reference
  • Global Properties
  • Pulse Generator
  • Output (TTL and CML)
  • Output (CML only)
  • Input
  • Event Mapping
  • Database Events
  • Data Buffer Rx
  • Data Buffer Tx